For this study synchrotron radiation micro-tomography, a non-destructive three-dimensional imaging technique, is employed to investigate an entire microelectronic package with a cross-sectional area of 16 x 16 mm. Due to the synchrotron's high flux and brightness the sample was imaged in just 3 min with an 8.7 µm spatial resolution.
Synchrotron radiation micro-tomography (SRµT) is a non-destructive three-dimensional (3D) imaging technique that offers high flux for fast data acquisition times with high spatial resolution. In the electronics industry there is serious interest in performing failure analysis on 3D microelectronic packages, many which contain multiple levels of high-density interconnections. Often in tomography there is a trade-off between image resolution and the volume of a sample that can be imaged. This inverse relationship limits the usefulness of conventional computed tomography (CT) systems since a microelectronic package is often large in cross sectional area 100-3,600 mm2, but has important features on the micron scale. The micro-tomography beamline at the Advanced Light Source (ALS), in Berkeley, CA USA, has a setup which is adaptable and can be tailored to a sample's properties, i.e., density, thickness, etc., with a maximum allowable cross-section of 36 x 36 mm. This setup also has the option of being either monochromatic in the energy range ~7-43 keV or operating with maximum flux in white light mode using a polychromatic beam. Presented here are details of the experimental steps taken to image an entire 16 x 16 mm system within a package, in order to obtain 3D images of the system with a spatial resolution of 8.7 µm all within a scan time of less than 3 min. Also shown are results from packages scanned in different orientations and a sectioned package for higher resolution imaging. In contrast a conventional CT system would take hours to record data with potentially poorer resolution. Indeed, the ratio of field-of-view to throughput time is much higher when using the synchrotron radiation tomography setup. The description below of the experimental setup can be implemented and adapted for use with many other multi-materials.
In the microelectronics field, as in many other fields, non-destructive evaluation at the micrometer scale is necessary when characterizing samples. Specifically for the microelectronics industry there is interest in probing 3D microelectronics packages, containing multi-levels and multi-materials, and identifying failures in packages during thermal, electrical, and mechanical stressing of components. Around the world synchrotron radiation facilities have designated tomography and diffraction beamlines that are used for failure analysis of microelectronic packages. Some examples of this are imaging void formation caused by electromigration1-3, evaluating mechanisms for tin whisker growth4,5, in situ observations of undercooling and anisotropic thermal expansion of tin and intermetallic compounds (IMCs)6,7, in situ observation of solidification and IMC formation8-10, anisotropic mechanical behavior and recrystallization of tin and lead free solders10, voids in flip chip bumps, and in situ observations of Ag-nanoink sintering11. All of these studies have further advanced the understanding and development of components in the microelectronic industry. However, many of these studies have focused on small regions within the package. More information could be gleaned from testing and characterizing the full size package using high resolution SRµT in order to further their development.
The electronic packages being produced now contain multiple layers of interconnects. These packages and devices are growing more and more complex which calls for a 3D solution for non-destructive evaluation with regard to failure analysis, quality control, reliability risk assessment, and development. Certain defects require a technique that can detect features less than 5 µm in size, which include voids and cracks forming inside copper substrate vias, identifying non-contact open and nonwet solder pads in multilevel packaging12, locating and quantifying voids in ball grid arrays (BGAs) and C4 solder joints. During the substrate assembly process these types of defects must be identified and monitored extensively to avoid unwanted failures.
Currently CT systems using laboratory-based sources, also known as tabletop, are able to provide as high as ~1 µm spatial resolution, and are being used to isolate failures in multilevel packages with promising results. However, tabletop CT systems have some limitations when compared to SRµT setups13,14. Tabletop systems are limited to only imaging a certain density range of materials since they usually only contain one or two x-ray source spectrums. Also through-put-time (TPT) remains long for conventional tabletop CT systems requiring several hours of data acquisition time per 1-2 mm2 region of interest, which can limit its usefulness; for instance, analyzing failures in Through Silicon Vias (TSV), BGAs or C4 joints often require acquiring multiple Field of Views (FoV) or regions of interest at high resolution within the sample, resulting in total TPT of 8-12 hours, which is a show stopper for conventional tabletop CT systems when multiple samples have to be analyzed. Synchrotron radiation provides much higher flux and brightness than conventional x-ray sources, resulting in much faster data acquisition times for a given region of interest. Although SRµT does allow for more flexibility with respect to types of materials that can be imaged and sample volume, it does have limitations, which are specific to the synchrotron source and setup used, specifically maximum acceptable thickness and sample size. For the SRµT setup at the ALS the maximum cross-sectional area that can be imaged is <36 x 36 mm and the thickness is limited by the energy range and flux available and is material specific.
This study is used to demonstrate how SRµT can be utilized to image an entire multi-level system in package (SIP) with high resolution and low TPT (3-20 min) for use in inspecting 3D semiconductor packages. More details on comparing tabletop CT's to Synchrotron Source CT's can be found in references13,14.
Experimental Overview & Beamline 8.3.2 Description:
There are synchrotron facilities available for tomography experiments around the world; most of these facilities require submission of a proposal where the experimentalist describes the experiment, as well as its scientific impact. The experiments described here were all performed at the ALS at Lawrence Berkeley National Laboratory (LBNL) at beamline 8.3.2. For this beamline there are two energy mode options: 1) monochromatic in the energy range ~7-43 keV or 2) polychromatic "white" light where the entire available energy spectrum is used when scanning high density materials. During a typical scan at beamline 8.3.2 a sample is mounted on a rotational stage where x-rays penetrate the sample, then the attenuated x-rays are converted into visible light through a scintillator, magnified by a lens, and then projected onto a CCD for recording. This is done while the sample rotates from 0 to 180° producing a stack of images that is reconstructed to obtain a 3D view of the sample with micrometer resolution. The resulting tomographic dataset size ranges from ~3-20 Gb depending on the scan parameters. Figure 1 shows a schematic of the hutch where the sample is scanned.
The following protocol presented here describes the experimental setup, data acquisition, and processing steps required for imaging an entire microelectronic package, but the steps can be modified to image a variety of samples. The modifications depend on the sample size, density, geometries, and features of interest. Tables 1 and 2 present the resolution and sample size combinations available at beamline 8.3.2 (ALS, LBNL, Berkeley, CA). For the microelectronic package investigated here the sample was imaged using a polychromatic ("white") beam, which was selected due to the thickness and high-density of the sample's components. The sample was mounted in the horizontal orientation on a chuck mount, this orientation allowed for the entire sample to fit within the height of the beam, which is parallel with a height of ~4 mm and width of ~40 mm, therefore only requiring one scan to capture the entire sample.
Note: Protocol details described below were written specifically for work at beamline 8.3.2 at the ALS, Berkeley, CA. Adaptations may be required for work at other synchrotron facilities, which can be found around the world. Appropriate safety and radiation training is required for running experiments at these facilities and the guidelines for training can be found on each individual synchrotron facility's website. Any changes or updates to the tomography protocol (ALS, LBNL, Berkeley, CA) can be found on the beamline manual15. Details on the tomography process can be found in Reference16. The beamline scientists are available to answer any questions and will facilitate the experimental setup.
1. Steps for Performing Tomography Scans at Beamline 8.3.2 (ALS, LBNL)
2. Steps for Performing Tomographic Data Processing
The images captured using tomography occur due to the differential absorption of x-rays in the solder interconnects, metallic traces, and other materials in the microelectronic package as a function of the different attenuation lengths and thickness of these multi-materials. The SIP package consisted of a silicon die attached to a ceramic substrate with first level interconnect (FLI) flip chip C4 solder balls of approximately 80 µm diameter; mid-level interconnect (MLI) solder balls of approximately 350 µm connecting this substrate to an FR4 epoxy circuit board; and second level interconnect (SLI) BGA solder balls of approximately 650 µm on the back side of the circuit board. Figure 2 shows a schematic of the sample when it is placed in the horizontal orientation; this orientation was selected in order to fit the entire sample in the field of view for one scan. Figure 3 shows the 3D images from the same sample, an entire package, which was imaged in one scan with low TPT (Table 2). This data was analyzed and prepared using Avizo. For the microelectronic packages an angular increment of 0.175° was selected resulting in 1,025 images over 180 degrees. In Figure 3A the plate through holes, copper vias, and some of the substrate are visible. Figure 3B zooms in on a region of interest showing one corner of the field programmable gate array (FPGA) die and substrate. This shows how quickly the individual components of an entire multilevel package can be inspected. Figure 4 demonstrates the features detected with SRµT in a FPGA SIP package. Here the circuit board, VIA's, silicon die, both substrates, and all levels of interconnects are discernible. Figures 5 and 6 demonstrate the use of tomography data to visualize features in 3D, where two different views of the interconnects are displayed. Figure 6 shows a 3D image of the vertically scanned CPU die package with FLI and MLI connections. Due to the vertical scan orientation the entire samples was not captured in one scan, in order to image the entire sample in this orientation tiling would be necessary. Figure 6B shows a 2D tomographic slice magnified; here the image quality is sufficient to observe cracks within a solder ball, which were created during extended thermal cycling prior to imaging.
Figure 1. Schematic showing tomography setup. Schematic of the hutch at beamline 8.3.2 at the Advanced Light Source (Lawrence Berkeley National Laboratory, Berkeley CA USA). (Figure taken from 8.3.2 Microtomography Manual, and can be accessed at: http://microct.lbl.gov/manual) Please click here to view a larger version of this figure.
Figure 2. Steps for reconstructing data. Schematic showing the steps to get a final 3D reconstructed image of a sample from the tomography setup. The sample here is a 16 x 16 mm SIP package being imaged in the horizontal orientation. Please click here to view a larger version of this figure.
Figure 3. 3D volume rendering of package. 3D rendering of an entire FPGA SIP package imaged with 8.7 µm resolution and a scan time of 3 min (A) shows the entire package, and (B) zoomed-in view of a region of the package showing one corner of the FPGA substrate and the circuit board interconnections.13 Please click here to view a larger version of this figure.
Figure 4. Tomographic image showing a cross-section of the package. 2D reconstructed slice taken through the FPGA SIP package. This sample was imaged with 4.5 µm resolution and a scan time of 20 min. The silicon die, underfill, both substrates, and all levels of interconnects can be observed.13 Please click here to view a larger version of this figure.
Figure 5. 3D volume rendering of the three interconnect levels. Segmented 3D image showing the entire SIP package with an 8.7 µm resolution (3 min scan time). This shows the three levels of interconnects (FLI, MLI, and SLI).13 Please click here to view a larger version of this figure.
Figure 6. Visible pores identified in a solder ball. (A) 3D reconstructed image of the vertically scanned CPU die package with FLI and MLI solder connections. (B) Zoomed in region of a 2D reconstructed slice, showing a MLI solder ball with a large center void and cracks caused during intentional thermal stress testing.13 Please click here to view a larger version of this figure.
Movie 1. Tomography images in 3D and 2D of the package (right click to download). This movie shows the 3D volume rendering of the 16 x 16 mm2 package from different perspectives. Then pans through the different slices to show internal information from within the package.
PCO.4,000 (4,008×2,672) | PCO.Edge (2,560×2,160) [Optique Peter*] | |||
Lens | Pixel (μm) | Field of view (mm) | Pixel (μm) | Field of view (mm) |
20X* | — | — | 0.33 | 0.8 |
10X | 0.9 | 3.6 | 0.69 | 1.7 |
5X | 1.8 | 7.2 | 1.3 | 3.3 |
2X | 4.5 | 18 | 3.25 | 8.3 |
1X | 9 | 36 | 6.5 | 16.6 |
Table 1. Details showing the cameras and lenses available at ALS beamline 8.3.2.
Source | Resolution Option | Camera/Lens Mag. | Pixel Size (µm) | FOV Width (mm) | FOV Height (mm) | Image Time TPT (min) | FOV/TPT (mm2/min) |
Synchrotron ALS BL 8.3.2 | low | A/1X | 8.7 | 36 | 6 | 3 | 72 |
low | B/1X | 6.5 | 16.6 | 6 | 3 | 33.2 | |
med | B/2X | 3.3 | 8.3 | 6 | 3 | 16.6 | |
med | A/2X | 4.5 | 18 | 6 | 20 | 5.4 | |
high | B/5X | 1.3 | 3.3 | 2.8 | 5 | 1.84 | |
high | B/10X | 0.65 | 1.7 | 1.4 | 11 | 0.22 | |
Lab-Based Source MicroXCT-200 | high | – | 1.5-2 | 1.5-2 | 1.5-2 | 180-240 | ~0.02 |
Table 2. Summary of resolutions, field of view, and imaging time for different cameras and lens options.
All of the steps described in the protocol section are critical to obtaining high-resolution images of multi-scale and multi-material samples. One of the most critical steps is the sample mounting and the focusing of optics, which are vital to obtaining quality images that can be used for quantification. Specifically, even slight movement of the sample would cause artifacts in the reconstructed image and defocusing would cause deterioration in resolution. To avoid issues with image quality it is important to reconstruct a test image, which can take place simultaneously while the next sample scans. This will help identify any issues or problems that may have occurred during the scan setup. If there are problems with the reconstructed image it might be necessary to re-scan the sample paying careful attention to sample mounting and alignment. During setup other issues may arise, such as errors with Labview, problems with the sample stage motor, or the absence of the x-ray beam. There are detailed steps for troubleshooting on the beamline's manual, which can be found on beamline website. Consult the beamline scientists to discuss further options for improving image quality or if the experimentalist comes across a problem not covered in the manual.
All of the figures shown here highlight the benefits of using SRµT to image an entire multi-level microelectronic package in only a few minutes with high spatial resolution and the ability to perform analysis on specific features within the sample non-destructively. For the samples imaged here the reconstruction time took under an hour. The wide energy spectrum at the ALS enables imaging of both high and low atomic number elements with the appropriate filtering. This allows for quantification of cracks, voids, delamination, defects, and much more. For several of the samples imaged here the continuous tomography mode aided in the fast data acquisition times. Although there is a wide range of materials and volumes that can be imaged using SRµT there are several limitations due to the available energy range for the ALS synchrotron facility. Specifically, the thickness of highly dense materials can be constrained.
This high-resolution capability of the synchrotron source CT system provides valuable information for both failure analysis and assembly process development. In contrast the tabletop CT system's relatively low brightness cannot allow for selection of a monochromatic energy and has difficulty highlighting defects in the presence of copper or solder surrounding features. The ability of a tomography technique to accommodate large sample sizes with faster TPT time is of the upmost importance to the semiconductor industry. The results obtained using SRµT suggest a path forward for new applications in microelectronics14. Overall there's a wide range of possibilities in this field for future work, specifically investigating these multi-material multi-scale microelectronic packages under in situ conditions, such as cycling temperature and cyclic loading.
The authors have nothing to disclose.
The LLNL portion of this work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344. The Intel Corporation authors would like to thank Pilin Liu, Liang Hu, William Hammond, and Carlos Orduno from Intel Corporation for some of the data collection and helpful discussions. The Advanced Light Source is supported by the Director, Office of Science, Office of Basic Energy Sciences, of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231.
Beamline 8.3.2 | Advanced Light Source, Berkeley, CA, USA | http://microct.lbl.gov/ |