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Ingenieurwesen

硅上半圆柱空隙锗外延层位错还原的理论计算和实验验证

Published: July 17, 2020
doi:
10.3791/58897
, , ,
1Department of Materials Engineering,The University of Tokyo, 2Department of Electrical and Electronic Information Engineering,Toyohashi University of Technology, 3Department of Materials Science and Engineering,Massachusetts Institute of Technology

Summary

提出了降低硅上半圆柱空隙的锗外延层螺纹位错（TD）密度的理论计算和实验验证。给出了基于TD与表面相互作用的计算方法，通过像力、TD测量和透射电子显微镜对TD的观测。

Abstract

降低硅（Si）上外延锗（Ge）的螺纹位错密度（TDD）是实现单片集成光子电路的最重要挑战之一。本文介绍了一种降低TDD的新模型的理论计算和实验验证方法。理论计算方法描述了基于TDs与选择性外延生长（SEG）的非平面生长表面在位错成像力方面的相互作用的螺纹位错（TDs）的弯曲。计算表明，SiO2 掩模上空隙的存在有助于降低TDD。采用超高真空化学气相沉积法和TD观察生长的锗（Ge）SEG通过蚀刻和横截面透射电子显微镜（TEM）对生长的Ge进行实验验证。强烈建议TDD降低是由于SiO2 SEG掩模和生长温度上存在半圆柱形空隙。为了进行实验验证，由于Ge层的SEG及其聚结作用，形成了具有半圆柱形空隙的外延Ge层。实验得到的TDDs基于理论模型再现了计算出的TDD。横断面透射电镜观察表明，TD的终止和生成都发生在半圆柱形空隙处。平面透射电镜观测揭示了具有半圆柱形空隙的Ge中TD的独特行为（即TD弯曲以平行于SEG掩模和Si衬底）。

Introduction

Si上的外延锗作为有源光子器件平台引起了广泛兴趣，因为Ge可以检测/发射光通信范围（1.3-1.6μm）内的光，并且与Si CMOS（互补金属氧化物半导体）加工技术兼容。然而，由于Ge和Si之间的晶格失配高达4.2%，因此在Si上的Ge外延层中以~109 / cm2的密度形成螺纹位错（TDs）。由于TD在Ge光电探测器（PD）和调制器（MOD）中充当载流子生成中心，在激光二极管（LDs）中充当载流子复合中心，因此锗光子器件的性能会因TD而恶化。反过来，它们会增加PD和MOD1，2，3中的反向泄漏电流（J泄漏）和LDs4，5，6中的阈值电流（J th）。

据报道，已经有各种尝试来降低Si上Ge中的TD密度（TDD）（补充图1）。热退火刺激TD的运动，导致TDD降低，通常为2 x 107 / cm2。缺点是Si和Ge可能混合，并且掺杂剂在Ge中扩散，例如磷7，8，9（补充图1a）。SiGe分级缓冲层10，11，12增加了临界厚度并抑制了TD的产生，导致TDD降低，通常为2 x 106/cm2。这里的缺点是厚缓冲器会降低Ge器件和下方Si波导之间的光耦合效率（补充图1b）。纵横比捕获 （ART）13，14，15 是一种选择性外延生长 （SEG） 方法，通过将 TD 捕获在厚 SiO 2 沟槽的侧壁上来降低 TD，通常为 <1 x 10 6/cm 2。ART方法使用较厚的SiO 2掩模来降低Ge中的TDD，而不是SiO 2掩模，SiO2掩模远高于Si，并且具有相同的缺点（补充图1b，1c）。Si柱晶种上的Ge生长和退火16，17，18与ART方法相似，通过高纵横比Ge生长使TD捕获达到<1 x 105/cm2。然而，用于Ge聚结的高温退火在补充图1a-c（补充图1d）中具有相同的缺点。

为了在硅上实现低TDD的Ge外延生长，而不受上述方法的缺点，我们根据迄今为止在SEG Ge生长7，15，21，22，23中报告的以下两个关键观察结果，提出了聚结诱导的TDD还原19，20：1）TD弯曲成垂直于生长表面（通过横截面透射电子显微镜（TEM）观察），2）SEG Ge层的聚结导致在SiO2掩模上形成半圆柱形空隙。

我们假设TD由于生长表面的成像力而弯曲。在Si上的Ge的情况下，像像力分别在距离自由表面1 nm处产生1.38 GPa和1.86 GPa的螺杆位错和边缘位错的剪切应力19。计算出的剪切应力明显大于Ge24中报告的60°位错的Peierls应力0.5 GPa。该计算预测了Ge SEG层的TDD减少，并且与SEG Ge增长19非常吻合。对TD进行TEM观察以了解Si20上所呈现的SEG Ge生长中的TD行为。镜像力诱导的TDD还原没有任何热退火或厚缓冲层，因此更适合光子器件应用。

本文介绍了TDD还原方法的理论计算和实验验证的具体方法。

Protocol

1. 理论计算程序 计算TD的轨迹。在计算中，假设 SEG 掩码足够薄，可以忽略 ART 对 TDD 减少的影响。确定生长表面并用方程表示。例如，使用时间演化参数 n = i、SEG Ge 高度 （h i） 和 SEG Ge 半径 （r i） 表示 SEG Ge 层圆形横截面的时间演变，如补充视频 1a 和等式 （1） 所示：<img alt="Equation 4" src="/files/ftp_upload/58897/58897eq4.jpg" style="opacity:…

Representative Results

理论计算 图3显示了6种聚结Ge层中TD的计算轨迹：在这里，我们将孔径比（APR）定义为W窗口/（W窗口+ W掩模）。图3a显示了APR = 0.8的圆形SEG原点聚结Ge。在这里，2/6 TD 被困住。图3b显示了APR = 0.8的{113}面SEG原点聚结Ge。在这里?…

Discussion

在本工作中，实验显示了4 x 107 / cm2 的TDD。为了进一步降低TDD，协议中主要有2个关键步骤：SEG掩膜制备和外延Ge生长。

图4所示的模型表明，当APR，W窗口/（W窗口+ W掩模）小至0.1时，TDD可以降低到107 / cm2在聚结Ge中。为了进一步降低TDD，应准备具有较小APR的SEG口罩。如步骤2.1.2所述，W窗口?…

Offenlegungen

The authors have nothing to disclose.

Acknowledgements

这项工作得到了日本文部科学省（MEXT）的日本科学促进会（JSPS）KAKENHI（17J10044）的资助。制造工艺得到了日本文部科学省“纳米技术平台”（项目编号12024046）的支持。作者要感谢东京大学的K. Yamashita先生和平田S. Ms. Hirata女士在TEM观测方面的帮助。

Materials

AFM SII NanoTechnology SPI-3800N
BHF DAIKIN BHF-63U
CAD design AUTODESK AutoCAD 2013 Software
CH3COOH Kanto-Kagaku Acetic Acid for Electronics
CVD Canon ANELVA I-2100 SRE
Developer ZEON ZED
Developer rinse ZEON ZMD
EB writer ADVANTEST F5112+VD01
Furnace Koyo Thermo System KTF-050N-PA
HF, 0.5 % Kanto-Kagaku 0.5 % HF
HF, 50 % Kanto-Kagaku 50 % HF
HNO3, 61 % Kanto-Kagaku HNO3 1.38 for Electronics
I2 Kanto-Kagaku Iodine 100g
Photoresist ZEON ZEP520A
Photoresist remover Tokyo Ohka Hakuri-104
Surfactant Tokyo Ohka OAP
TEM JEOL JEM-2010HC
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Referenzen

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Tags

Dislocation ReductionGermanium Epitaxial LayersSemicylindrical VoidsSiliconThreading Dislocation DensitySelective Epitaxial GrowthBoron-doped P-siliconSilicon DioxidePhotoresistBuffered Hydrofluoric AcidGermanium Growth

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Yako, M., Ishikawa, Y., Abe, E., Wada, K. Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon. J. Vis. Exp. (161), e58897, doi:10.3791/58897 (2020).
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