The fabrication process and experimental characterization techniques relevant to single-electron pumps based on silicon metal-oxide-semiconductor quantum dots are discussed.
As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization.
Silicon is the material of choice for most of the modern microelectronics. Its properties, combined with advanced lithographic techniques, have allowed the semiconductor industry to achieve very large-scale integration and deliver billions of transistors per chip. The metal-oxide-semiconductor (MOS) technology1 has been the key of this relentless technological progress2. In brief, it is based on a selectively doped Si substrate which is thermally oxidized to grow a high quality SiO2 gate oxide on which a metal gate electrode is deposited. Recently, it has been shown that the use of a stack of gate oxides could be beneficial3 . While present industry standards have reached minimum feature sizes for gate lengths below 20 nm, it is becoming increasingly evident that, at this level of miniaturization, detrimental quantum mechanical phenomena come into play that may complicate further downscaling4.
Remarkably, silicon is also an excellent host material to exploit the quantum properties of the electron charge and spin5. This has broadened its range of applicability to entirely new fields such as quantum computing6 and quantum electrical metrology7. Among other approaches5, the use of a multi-gate MOS technology8,9 has led to electrostatically-defined quantum dots (QD) whose occupancy can be controlled down to single-electron level10. Unlike the conventional MOS process where just one gate per transistor is needed1, these QDs are defined via a three-layer stack of Al/AlyOx gates which are used to selectively accumulate electrons at the Si/SiO2 interface, as well as provide lateral and vertical confinement11.
Although these devices had been originally developed for quantum computing applications, they have also recently shown promising performances as metrological tools12,13. In the field of quantum electrical metrology, a long-standing goal is the redefinition of the unit ampere in terms of the elementary charge (e) 14. In particular, the emphasis is on the realization of nano-scale charge pumps to clock the transfer of individual electrons timely and accurately. These devices generate macroscopic quantized electric currents, I=nef, where f is the frequency of an external driving oscillator and n is an integer. To date, the best performance has been achieved with a GaAs-based pump by yielding a current in excess of 150 pA with a relative uncertainty of 1.2 parts per million15. Recently, silicon MOS QDs have also stood out for the implementation of highly accurate single-electron pumps thanks to the capability of finely tuning the charge confinement13.
Here, we discuss the protocol used for the fabrication of silicon MOS QDs. Furthermore, the cryogenic set-up used to test the integrity of the devices after fabrication and the one to perform charge pumping experiments are described. Finally, representative measurements of quantized electric current are reported.
本文报道的协议描述的技术来制造硅的MOS量子点,以及实验步骤,以测试它们的功能完整性和操作它们作为单电子泵。值得注意的是,通过调整栅设计,在同一个制造工序,可以采用,以产生设备适合于量子位的读出和控制17,以及电荷抽12,13。我们注意到,许多在本文中所引述的工艺参数可以根据所使用的制造工具而变化(校准,使或模型),以及在硅基板(厚度和背景掺杂浓度)的类型。量如光刻曝光剂量或开发时间,蚀刻或氧化的持续时间,必须仔细校准和测试,以确保可靠的产率。此外,关键的是要避免因使用不同的过程相同的制造工具所产生的交叉污染。为此,一些铬的itical步骤进行的设备专用于硅处理,如金属蒸发器,氧气转炉和HF浴。
更一般地,硅被绘制一个越来越大的兴趣作为首选材料来实现电荷泵18-20。这部分是由于使用的是工业兼容的硅工艺实现了新的基于量子的电流标准的吸引力角度。这将受益于成熟的,可靠的集成技术的可扩展性,并行和驾驶开销。重要的是,一个完整的互补MOS(CMOS)技术,无传统的金属作为栅极材料,已经显示出大大降低背景电荷波动单电子器件21。这种波动可以实现计量精度有害的。
这里所讨论的协议被限制为实现MOS纳米器件与金属栅极。因此,为了achie已经充分工业兼容性和减少电荷的波动,这将需要修改的栅极沉积技术,并使用高度掺杂的多晶硅作为栅极材料。
总之,这里所讨论的MOS QD泵最近结合硅的技术优势,在精确的电流产生13方面是非常好的性能。这源于设计和制造方法,该方法允许一个堆叠多个栅层导致紧凑和灵活的系统的高的灵活性。与减少的背景电荷波动的潜在点起来的静电禁闭得到的细调谐设置了舞台,以克服在其他半导体中观察到的主要挑战泵22,23。
The authors have nothing to disclose.
我们感谢KY谭P.见和GC Tettamanzi进行了有益的讨论。我们承认,从澳大利亚研究理事会(批准号:DP120104710),芬兰科学院(批准号:251748,135794,272806)的资金支持,并支持澳大利亚国家制造工厂的设备制造。 AR确认来自新南威尔士大学的早期职业研究员补助金计划的资金支持。设施和技术支持由阿尔托大学在纳米加工Micronova中心规定也承认。
Silicon wafers | TOPSIL | 4 inch | |
Electron-beam lithography machine | Raith gmbh | Raith 150two | |
E-beam resist | MicroChem gmbh | PMMA | |
Photoresist | MicroChem gmbh | nLOF2020 | |
Mask aligner | Quintel | Q6000 | |
Photoresist developer | MicroChem gmbh | AZ826MIF |